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acpl-m61t automotive wide operating temperature aec-q 00 compliant 0mbd digital optocoupler data sheet features ? high temperature and reliability canbus communic- ation interface for automotive application. ? 15 kv/ m s high common-mode rejection at v cm = 1000 v ? compact, auto-insertable so5 packages ? wide temperature range: -40c ~ 125c ? high speed: 10mbd (typical) ? low led drive current: 6.5ma (typ) ? low propagation delay: 100ns (max) ? worldwide safety approval: ? ul 1577, 3750 vrms/1 min. ? csa file ca88324, notice #5 ? qualifed according to aec-q100 test guidelines applications ? automotive canbus communications interface ? high temperature digital signal isolation ? micro-controller interface ? digital isolation for a/d, d/a conversion description this small outline wide operating temperature, high cmr, high speed, logic gate optocoupler is a single channel device in a fve lead miniature footprint. the acpl-m61t optically coupled gates combine a algaas light emitting diode and an integrated high gain photo detector. the output of the detector ic is an open- collector schottky-clamped transistor. the internal shield provides a guaranteed common mode transient immunity specifcation of 15,000 v/s at v cm =1000v. this optocoupler is suitable for use in automotive high speed communications logic interfacing with low propa - gation delays, input/output bufering and is recommend - ed for use in high operating temperature environment. this unique design provides maximum ac and dc circuit isolation while achieving ttl compatibility. the optocou - pler ac and dc operational parameters are guaranteed from -40c to 125c. functional diagram v cc gnd 1 3 6 5 4 anode cathode v o caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product
schematic shield 6 5 4 1 3 use of a 0.1 f bypass capacitor must be connected between pin s 6 and 4 (see note 1). i f i cc v cc v o gn d i o + - truth table (positive logic) led on off outpu t l h 8.27 (0.325) 2.0 (0.080) 2.5 (0.10) 1.3 (0.05) 0.64 (0.025) 4.4 (0.17) land pattern recommendation ordering information acpl-m61t is ul recognized with 3750 vrms for 1 minute per ul1577 and is approved under csa component accep - tance notice #5, file ca 88324. part number option package surface mount gull wing tape & reel ul 5000 vrms/1 minute rating iec/en/din en 60747-5-2 quantity rohs compliant non rohs compliant acpl-m6 t -000e no option so-5 00 per tube -500e -500 x x x 500 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: ACPL-M61T-500e to order product of mini-fat surface mount 5-pin package in tape and reel packaging with rohs compliant. example 2: acpl-m61t to order product of mini-fat surface mount 5-pin package in tube packaging and non rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. remarks: the notation #xxx is used for existing products, while (new) products launched since 15th july 2001 and rohs compliant option will use -xxxe.
package outline drawings acpl-m61t small outline so-5 package (jedec mo-155) m61t yww ee 6 5 4 3 1 7.0 0.2 (0.276 0.008) 2.5 0.1 (0.098 0.004) 0.102 0.102 (0.004 0.004) v cc v out gnd cathode anode 4.4 0.1 (0.173 0.004) 1.27 (0.050) bsc 0.20 0.025 (0.008 0.001) 0.71 (0.028) min. 0.4 0.05 (0.016 0.002) 3.6 0.1* (0.142 0.004) dimensions in millimeters (inches) * maximum mold flash on each side is 0.15 mm (0.006) note: floating lead protrusion is 0.15 mm (6 mils) max. 7 o max. max. lead coplanarity = 0.102 (0.004) extended datecode for lot tracking solder refow temperature profle 0 time (seconds) temperature ( ? c) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160 ? c 140 ? c 150 ? c peak temp. 245 ? c peak temp. 240 ? c peak temp. 230 ? c soldering tim e 200 ? c preheating tim e 150 ? c, 90 + 30 sec. 2.5 ? c 0.5 ? c/sec. 3 ? c + 1 ? c/ - 0.5 ? c tight typical loose room temperature preheating rate 3 ? c + 1 ? c/ - 0.5 ? c/sec. reflow heating rate 2.5 ? c 0.5 ? c/sec. note: non-halide fux should be used.
regulatory information the acpl-m61t is pending approval by the following organizations: ul approved under ul 1577, component recognition program up to v iso = 3750 v rms expected prior to product release. csa approved under csa component acceptance notice #5. insulation and safety related specifcations parameter symbol acpl-m61t units conditions minimum external air gap (clearance) l(0) 5 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (creepage) l(0) 5 mm measured from input terminals to output terminals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.08 mm through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. tracking resistance (comparative tracking index) cti 75 v din iec /vde 00 part isolation group (din vde0 09) iiia material group (din vde 0 09) recommended pb-free ir profle 217 c ramp-dow n 6 c/sec. max. ramp-up 3 c/sec. max. 150 - 200 c 260 +0/-5 c t 25 c to peak 60 to 150 sec. 20-40 sec . time within 5 c of actual peak temperature t p t s preheat 60 to 180 sec. t l t l t smax t smin 25 t p time temperature no tes: the time from 25 c to peak temperature = 8 minutes max. t smax = 200 c, t smin = 150 c note: non-halide fux should be used.
5 absolute maximum ratings parameter symbol min. max. units note storage temperature t s -55 5 c operating temperature t a -0 5 c lead soldering cycle temperature 60 c time 0 sec input current average i f(avg) 0 ma (50% duty cycle, ms pulse width) peak i f(peak) 0 ma (<= us pulse width, 00ps) transient i f(trans) 00 ma reversed input voltage v r 5 v input power dissipation p i 0 mw output power dissipation p o 85 mw output collector current i o 50 ma supply voltage (pins 6- ) v cc -0.5 7 v output voltage (pins 5- ) v o -0.5 7 v recommended operating conditions parameter symbol min. max. units supply voltage v cc .5 5.5 v operating temperature t a -0 5 c input current, low level i fl * 0 50 fa input current, high level i fh 5 5 ma fan out (rl = k) n 5 ttl loads output pull-up resistor r l 0 ,000 * the of condition can also be guaranteed by ensuring that v f (of ) 0.8volts electrical specifcations (dc) over recommended operating temperature t a = -40c to 125c, unless otherwise specifed. parameter symbol min. typ.* max. units conditions fig. note input threshold current i th 5 ma vcc = 5.5v, io ma, vo = 0.6v high level output current i oh 5.5 00 m a vcc = 5.5v, vo = 5.5v, vf = 0.5v low level output voltage v ol 0. 0.6 v vcc = 5.5v, i f = 6.5ma i ol (sinking) = ma , , 5 high level supply current i cch 7.0 0.0 ma vcc = 5.5v, i f = 0ma low level supply current i ccl 9.0 .0 ma vcc = 5.5v, i f = 0ma, input forward voltage v f .5 .5 .85 v t a =5 c, i f = 0ma .5 .5 .95 v i f = 0ma input reversed breakdown voltage bv r 5 v i r = 0 m a temperature coefcient of forward voltage d v f / d t a -.5 mv/ c i f = 0ma , *all typicals at ta = 25c, vcc = 5v.
6 switching specifcations (ac) over recommended temperature t a = -40c to 125c, v cc = 5.0 v, i f = 6.5ma unless otherwise specifed. parameter symbol min. typ. max. units test conditions fig. note propagation delay time to low output level t phl 6 75 ns t a =5 c r l = 50 c l = 5pf i f = 6.5ma 6, 7, 8 6 00 ns propagation delay time to high output level t plh 50 75 ns t a =5 c 6, 7, 8 5 00 ns propagation delay skew t psk 0 ns , 5 0, pulse width distortion | t phl - t plh | .5 5 ns 9 0 output rise time ( 0% - 90%) t rise ns 0 output fall time ( 0% - 90%) t fall 0 ns 0 common mode transient immunity at high output level |cm h | 5 0 kv/fs v cm = 000vp-p vo(min) = v i f = 0ma t a =5 c r l =50 7,9 common mode transient immunity at low output level |cm l | 5 0 kv/fs v cm = 000vp-p vo(max) = 0.8v i f = 6.5ma t a =5 c r l =50 8,9 *all typicals at t a = 25c, vcc = 5v. notes: 1. bypassing of the power supply line is required with a 0.1 f ceramic disc capacitor adjacent to each optocoupler. the total lead length between both ends of the capacitor and the isolator pins should not exceed 10 mm. 2. peaking circuits may produce transient input currents up to 40 ma, 50 ns maximum pulse width, provided average current does not exceed 20 ma. 3. device considered a two terminal device: pins 1 and 3 shorted together and pins 4, 5 and 6 shorted together. 4. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage 4500 v rms for 1 second (leakage detection current limit, i i-o 5 a). 5. the t plh propagation delay is measured from 3.25 ma point on the falling edge of the input pulse to the 1.5 v point on the rising edge of the output pulse. 6. the t phl propagation delay is measured from 3.25 ma point on the rising edge of the input pulse to the 1.5 v point on the falling edge of the output pulse. 7. cm h is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., v out > 2.0 v). 8. cm l is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., v out < 0.8 v). 9. for sinusoidal voltages, (|dv cm |/dt)max = p f cm v cm (p-p). 10. see application section; propagation delay, pulse-width distortion and propagation delay skew for more information. 11. t psk is equal to the worst case diference in t phl and/or t plh that will be seen between units at any given temperature within the worst case operating condition range. 12. input current derates linearly above 85c free-air temperature at a rate of 0.25 ma/c. 13. input power derates linearly above 85c free-air temperature at a rate of 0.375mw/c. 14. output power derates linearly above 85c free-air temperature at a rate of 0.475 mw/c. package characteristics parameter symbol min. typ. max. units test conditions fig. note input-output momentary withstand voltage* v iso 750 v rms rh 50%, t = min;t a = 5c input-output resistance r i-o 0 v i-o = 500 vdc input-output capacitance c i-o 0.6 pf f = mhz; v i-o = 0 vdc * the input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating refer to the iec/en/din en 60747-5-2 insulation characteristics table (if applicable), your equipment level safety specifcation, or avago technologies application note 1074, optocoupler input-output endurance voltage.
7 0 0.5 1 1.5 2 2.5 3 3.5 -60 -40 -20 0 2 0 4 0 6 0 8 0 100 120 140 t a - temperature - o c i oh - high level output current - ua v cc = 5.5v v o = 5.5v v f = 0.5v 0.1 0.2 0.3 0.4 0.5 -60 -40 -20 0 2 0 4 0 6 0 8 0 100 120 140 t a - temperature - o c v ol - low level output voltage - v v cc = 5.5v i f = 6.5m a i o = 6.4m a i o = 9.6m a i o = 12.8m a i o = 16m a figure 5. low level output current vs. temperature figure 4. output voltage vs forward input current figure 3. input current vs forward voltage figure 2. low level output voltage vs. temperature figure 1. high level output current vs temperature 0.01 0.10 1.00 10.00 100.00 1.20 1.30 1.40 1.50 1.60 v f - forward voltage - volts i f - forward current - ma t a = 25 o c 0 10 20 30 40 50 60 -60 -40 -20 0 2 0 4 0 6 0 8 0 100 120 140 t a - temperature - o c i ol - low level output current - ma v cc = 5.0v v ol = 0.6v i f = 5ma i f = 10ma, 15m a 0 1 2 3 4 5 6 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 i f - forward input current - m a v o - output voltage - v v cc =5v t a = 25 o c r loa d = 350 ? r loa d = 4k ? r loa d = 1k ?
8 output v o monitoring node 1.5 v t plh t phl i f input v o output i f = 6.5 ma i f = 3.25 ma +5 v i f r l r m 0.1f bypass *c l *c l is approximately 15 pf which includes probe and stray wiring capacitance . input monitoring node pulse gen. z o = 50 ? t f = t r = 5 ns v cc gnd 1 3 6 5 4 figure 6. test circuit for t phl and t plh figure 8. propagation delay vs. pulse input current figure 7. propagation delay vs. temperature 0 20 40 60 80 100 120 -60 -40 -20 0 2 0 4 0 6 0 8 0 100 120 140 t a - temperature - o c tp - propogation delay - ns v cc i f t plh , r l t plh , r t phl r l = 5.0v = 6.5m a = 350 ? = 4k ? l = 350 ? 1k ? 4k ? = 1k ? t plh , r l 30 40 50 60 70 80 90 3 5 7 9 i f - pulse input current - m a t p - propogation delay - ns t phl r l = 350 ? 1k ? 4k ? t plh , r l = 350 ? t plh , r l = 1k ? t plh , r l = 4 ? v cc = 5.0v t a = 25 o c
9 figure 10. rise and fall time vs.temperature figure 9. pulse width distortion vs temperature 0 50 100 150 200 250 300 350 -60 -40 -20 0 2 0 4 0 6 0 8 0 100 120 140 t a - temperature - o c tr, tf - rise, fall time - ns v cc = 5.0v i f = 6.5m a r l = 4k ? r l =350 ? , 1 k ? , 4 k ? r l = 350 r l = 1k ? t rise t fall figure 11. test circuit for common mode transient immunity and typical waveforms v o 0.5 v v o (min.) 5 v 0 v switch at a: i f = 0 ma switch at b: i f = 6.5 ma v cm cm h cm l v o (max.) v cm (peak) v o +5 v 0.1 f bypass + _ 350 ? v ff 1 3 6 5 4 b a output v o monitoring node i f pulse generato r z o = 50 ? v cc gnd figure 12. temperature coefcient for forward voltage vs. input current -2.300 -2.200 -2.100 -2.000 -1.900 -1.800 0.1 1 1 0 100 i f - pulse input current - ma temperature coefficient - mv/ o c dvf/dt - forward voltage -10 0 10 20 30 40 -60 -40 -20 0 2 0 4 0 6 0 8 0 100 120 140 t a - temperature - o c pwd - pulse width distortion - ns v cc i f r l r l r l = 1k ? = 4k ? = 350 ? = 5.0v = 6.5m a
0 propagation delay, pulse-width distortion and propaga - tion delay skew propagation delay is a fgure of merit which describes how quickly a logic signal propagates through a system. the propagation delay from low to high (t plh ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. similarly, the propagation delay from high to low (t phl ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see figure 6). pulse-width distortion (pwd) results when t plh and t phl difer in value. pwd is defned as the diference between t plh and t phl and often determines the maximum data rate capability of a transmission system. pwd can be expressed in percent by dividing the pwd (in ns) by the minimum pulse width (in ns) being transmitted. typically, pwd on the order of 20-30% of the minimum pulse width is tolerable; the exact fgure depends on the particular ap - plication (rs232, rs422, t-1, etc.). propagation delay skew, t psk , is an important parameter to consider in parallel data applications where synchro - nization of signals on parallel data lines is a concern. if the parallel data is being sent through a group of op - tocouplers, diferences in propagation delays will cause the data to arrive at the outputs of the optocouplers at diferent times. if this diference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocou - plers. propagation delay skew is defned as the diference between the minimum and maximum propagation delays, either t plh or t phl , for any given group of optocou - plers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). as illustrated in figure 14, if the inputs of a group of optocouplers are switched either on or off at the same time, t psk is the diference between the shortest propagation delay, either t plh or t phl , and the longest propagation delay, either t plh or t phl . as mentioned earlier, t psk can determine the maximum parallel data transmission rate. figure 15 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through opto - couplers. the fgure shows data and clock signals at the inputs and outputs of the optocouplers. to obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. propagation delay skew represents the uncertainty of where an edge might be after being sent through an op - tocoupler. figure 15 shows that there will be uncertainty in both the data and the clock lines. it is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. from these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel applica - tion is twice t psk . a cautious design should use a slightly longer pulse width to ensure that any additional uncer - tainty in the rest of the circuit does not cause a problem. the t psk specifed optocouplers ofer the advantages of guaranteed specifcations for propagation delays, pulse-width distortion and propagation delay skew over the recommended temperature, and input current, and power supply ranges. figure 13. recommended ttl/lsttl to ttl/lsttl interface circuit. v cc 1 gnd 1 470 shiel d * diode d1 (1n916 or equivalent) is not required for units with open collector output. 6 5 4 390 ? 0.1 f bypass gnd 2 v cc 2 1 3 *d 1 5 v 5 v i f v f 2 1
figure 14. illustration of propagation delay skew C t psk figure 15. parallel data transmission example 50% 1.5 v i f v o 50% i f v o t psk 1.5 v data t psk inputs clock data outputs clock t psk for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies, limited in the united states and other countries. data subject to change. copyright ? 006 avago technologies limited. all rights reserved. obsoletes av0-060en av0 -0597en - august 7, 007

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